A receiver circuit that receives a digital signal is required to decide each data bit at an appropriate timing. For this reason, the receiver circuit often includes a signal recovery circuit (CDR: Clock Data Recovery) that recovers a clock and data from a received signal.
FIGS. 1A and 1B illustrate an example of a configuration and an operation of a signal recovery circuit. As illustrated in FIG. 1A, a signal recovery circuit 1 includes a phase detector 2, a charge pump 3, a loop filter 4, and a voltage controlled oscillator (VCO) 5. The phase detector 2 generates a phase detection signal PD indicating whether a clock signal CLK is delayed or advanced with respect to an input data signal “Data”. The charge pump 3 outputs current CP corresponding to the phase detection signal PD. The loop filter 4 averages the current CP output from the charge pump 3 so as to generate a control voltage. The VCO 5 generates a clock signal CLK of a frequency corresponding to the control voltage generated by the loop filter 4.
In the signal recovery circuit illustrated in FIG. 1A, when a clock signal is delayed with respect to an input data signal, the phase detector 2 outputs, for example, a phase detection signal of H-level. In this case, the oscillating frequency of the VCO 5 becomes higher, and then the phase of the clock signal with respect to the input data signal becomes closer to an optimal value. On the other hand, when the clock signal is advanced with respect to the input data signal, the phase detector 2 outputs, for example, a phase detection signal of L-level. In this case, the oscillating frequency of the VCO 5 becomes lower, and then the phase of the clock signal with respect to the input data signal becomes closer to the optimal value.
As a result, as illustrated in FIG. 1B, a rising edge of the clock signal is adjusted to be in the center of each bit of the input data signal, and the data signal is recovered by using the adjusted clock signal. At this point, a jitter of the data signal is removed.
As a related technology, a method for performing control such that a receiving-sensitivity control parameter that determines a receiving sensitivity of an optical receiver circuit is automatically located at an optimal position has been proposed (see, for example, Japanese Laid-open Patent Publication No. 2003-258924). An automatic-timing-adjustment decision circuit that realizes a speed up of an operation by reducing a load of a decision circuit has been proposed (see, for example, Japanese Laid-open Patent Publication No. 07-240762). An optical repeater that adjusts an optimal decision phase automatically so as to prevent a degradation of bit error rate characteristics has been proposed (see, for example, Japanese Laid-open Patent Publication No. 07-38505). A phase-locked loop for improving the accuracy of a phase/frequency detection has been proposed (see, for example, U.S. Pat. No. 5,694,088).
However, in the signal recovery circuit 1 of FIG. 1A, the phase of a clock signal is adjusted only according to a phase detection signal that indicates whether a clock signal is delayed or advanced with respect to an input data signal. Thus, it may take long time to optimize the phase of a clock signal. For example, even when a clock signal is greatly delayed or slightly delayed, the same phase detection signal is generated, so the amount of change in the oscillating frequency of the VCO 5 is the same. Thus, when the clock signal is greatly delayed, it takes long time to optimize the phase of the clock signal. On the other hand, when the clock signal is slightly delayed, the phase of the clock signal may go beyond an optimal point in the process of adjusting the phase of the clock signal.